The present invention relates to Design Based Metrology (DBM), and more specifically, to systems and methods for providing pattern recognition and edge correction in DBM that provides increased efficiency in locating devices on semiconductor wafers.
In semiconductor fabrication, routine measurements are made of critical devices or features throughout the manufacturing process flow. Critical Dimension Scanning Electron Microscopy (CD-SEM) is typically implemented to measure these features on the wafer since it is fast and relatively non-destructive. Measurement of such structures requires the ability of the CD-SEM to locate the general area of the structure(s) of interest, and also to recognize the structures on the wafer. As such, the devices are located based on the design layout. However, often times, the fabricated wafer differs considerably from the design layout due largely to the structural differences between the design layout and an actual fabricated device, and this can pose challenges for the automatic pattern recognition routine. DBM is one of the key enablers for Optical Proximity Correction (OPC)/process modeling to collect tens of thousands of wafer CD data. DBM also provides an alternative wafer-less route for metrology recipe creation to save time and engineering resources in producing in-line measurement recipes for development and manufacturing. Like manual recipes, DBM recipe measurement includes two steps. First, Pattern Recognition (PR) is implemented, in which wafer images are compared with given/stored images in order to register wafer location; in manual recipes these images are collected from wafers and stored in a database, and in DBM recipes they are simply small sections of design files stored in the same database. If PR is successful in registering the location, the second step is shifting from PR location by a prescribed offset to go to the target location (e.g., a device on which to render measurements) and measure CD at given edges. If PR fails, measurement also fails. As described herein, for DBM, the design layout provides the needed information for locating and measuring the devices. However, DBM recipes suffer low success rate when wafer image is significantly different from layout typically resulting in the inability to make a measurement.